The present invention relates to a method and apparatus for verifying the design and layout of an integrated circuit by applying a layer-based rule checking approach.
A highly specialized field, commonly referred to as xe2x80x9celectronic design automationxe2x80x9d (EDA), has evolved to handle the demanding and complicated task of designing and laying out integrated circuit (IC) semiconductor chips. In EDA, computers are extensively used to automate the design and layout process. Computers are ideally suited to performing tasks associated with the design process because computers can be programmed to reduce or decompose large, complicated functional requirements into a multitude of much smaller, simpler functions. Thereupon, the computer can be programmed to iteratively solve these simpler functions to attain a circuit design that would produce the desired results. A physical design tool is then commonly used to place and route the actual logic, physical pinouts, wiring, and interconnects according to the circuit design to produce a physical layout of the semiconductor chip. Indeed, it has now come to the point where the process has become so overwhelming that the next generation of IC chips cannot be designed and laid out without the help of computerized EDA systems.
However, before fabrication on the semiconductor chip begins, extensive testing must be performed to verify and check that the IC has been properly designed and physically laid out. Otherwise, it would be disastrous to find out that new IC chips being used in applications such as computer systems, telecommunications gear, consumer electronics, aviation equipment, medical devices, etc., were subsequently found to be defective. Hence, new designs and layouts are subjected to a host of rigorous testing procedures. One of these procedures calls for checking the physical layout to ensure that it meets certain well-established rules or guidelines. For instance, there may be a rule which stipulates that each of the metal interconnects must be at least of a certain width. If an interconnect is too narrow, it might become prone to breakage (e.g., through electromigration). Another rule might stipulate that two wires must be spaced at least a certain distance apart. If the wires are placed too closely together, the signals being conducted through those wires might interfere with one another or produce unwanted crosstalk. The wires might even, over time, touch and short circuit. Any violations of these established rules indicate a possible point of failure and are indicated to the designer. The designer can then take steps to modify the design and/or layout to correct and prevent fatal flaws in the IC chip.
Today, virtually all layouts are verified by applying a set of established rules to the layout data. The EDA verification software instructs the computer to apply a rule to specific portions of the layout design residing in a database. If that part of the layout meets the rule, then it passes the test. Otherwise, it fails, and the error is duly recorded. The next set of layout data is then read from the database, and the same rule is applied. This process is iteratively performed until all effected portions of the layout design have been tested against that rule. Thereupon, another rule is read. The portions of layout data are then successively read from the database, tested against this new rule, and any errors are recorded. This process repeats until all rules have been so checked against all of the relevant portions of the layout. Afterwards, all recorded errors or rule violations are displayed to the designer.
In the past, when semiconductor chips were simple, the verification process was relatively straightforward and quick. However, advances in semiconductor technology have led the way towards more versatile, powerful, and faster IC chips. The trend is towards even larger, more complex and sophisticated IC chips in an effort to meet and improve upon the demands imposed by state-of-the-art performance. Today, a single IC chip can contain upwards of millions of transistors. As the complexity, functionalities, speed, and size of these chips increase, it is becoming a much more difficult task to properly verify and test the next generation of chips. Furthermore, an increasing number of rules are now being applied to ever larger layouts. The end result is that, what used to take seconds to perform the verification process, can now take hours to perform. In the meantime, engineers and circuit designers must wait for the verification process to complete before they are able to continue working on the chip design. Often, several iterations of the design, layout, and verification process are required in order to optimize the semiconductor chip""s size, cost, heat output, speed, power consumption, and electrical functionalities. Consequently, the time it takes to perform the verification process can substantially increase the overall time it takes to finalize the IC chip and bring it to market. Time to market is of critical importance.
Thus, there is a need for some mechanism or method which would reduce the time it takes to perform the verification process. The present invention provides a unique, novel solution which greatly minimizes the time it takes to complete the verification process.
The present invention pertains to a computer implemented method for verifying the physical layout of new integrated circuit designs for semiconductor chips. Initially, the physical layout is stored in a database as a series of layers. A pre-defined set of rules are also stored. These rules specify certain dimensions and other criteria for checking to determine whether the new design has been properly laid out. The goal is to verify that the new layout design meets all the design rules. For each rule, one or more of the layers applicable to that particular rule is specified. Instead of reading a rule, reading the layout data, and then applying that rule to the layout data, the present invention performs a layer based approach whereby one or more layers are read and then the rules applicable to those layers identified and applied. This approach allows multiple rules to be checked with only a single read operation versus the prior art method which requires one read operation for each rule. Thus the present invention significantly minimizes the number of read operations required, which reduces the time it takes to perform the verification process.